1. Field of the Invention
The present invention relates to semiconductor devices having a dual gate electrode, and methods for making the same. More particularly, embodiments of the present invention relate to methods for forming a dual gate electrode of a semiconductor device that improve manufacturing productivity and semiconductor performance.
2. Background of the Invention
Generally, in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is typical of a semiconductor device, a device isolation layer is formed in a semiconductor substrate, then a gate electrode is formed on the corresponding semiconductor substrate, and then source/drain regions with dopant ions implanted in the semiconductor substrate between the gate electrode and the device isolation layer are formed.
A MOSFET of this type with p-type dopant ions implanted in the source/drain regions is referred to as a p-channel MOSFET (i.e., PMOS transistor), and a MOSFET of this type with n-type dopant ions implanted therein is referred to as a n-channel MOSFET (i.e., NMOS transistor).
As above, since the semiconductor device having both PMOS and NMOS transistors has two gate electrodes, this structure is called a dual-gate electrode structure. The role of a gate electrode can be widened through two gate electrodes, and one gate electrode can be replaced by the other gate electrode.
Further, the corresponding gate electrodes should have excellent conductivity and a high melting point, and should be easily patternable, and hence they are formed of polysilicon material which is easily doped with impurities at a high concentration and able to maintain a stable form in a subsequent thermal process that is performed at a high temperature.
FIGS. 1a to 1i are process cross sectional views sequentially showing a conventional method for forming a dual gate electrode of a semiconductor device.
First, as shown in FIG. 1a, a first polysilicon layer 110 for forming a gate electrode of one region (e.g., PMOS region) is formed over the entire surface of a semiconductor substrate 100 having a gate insulating layer (not shown) thereon by a method, such as deposition.
As the corresponding deposition, an LPCVD (Low Pressure Chemical Vapor Deposition) can be preferably used.
Next, as shown in FIG. 1b, a first photoresist pattern 120 is formed by a typical photo-lithography process so as to close and define the corresponding PMOS region. The corresponding photo-lithography process may consist of a series of process steps of photoresist solution coating, exposure, and developing.
Next, as shown in FIG. 1c, the first polysilicon layer 110 of the region not closed by the first photoresist pattern 120 but exposed is removed by etching by using the corresponding first photoresist pattern 120 as an etching mask.
Thereafter, as shown in FIG. 1d, the first photoresist pattern 120 used is removed, whereupon a plasma ashing method can be used.
Hence, a first gate electrode 110′ is formed in the PMOs region by the left first polysilicon layer.
Next, as shown in FIG. 1e, a second photoresist pattern 130 is formed by a photo-lithography process so as to close the formed first gate electrode 110′ at the top and protect it.
Thereafter, as shown in FIG. 1f, a second polysilicon layer 140 for forming a gate electrode is formed in an NMOS region, which is another region on the other side by a method such as LPCVD, and accordingly, the second polysilicon layer 140 is formed, especially, in the portion including the NMOS region not closed by the second photoresist pattern 130 but exposed.
As is next shown in FIG. 1g, the second photoresist pattern 130 is removed by a method, such as plasma ashing.
Next, as shown in FIG. 1h, a third photoresist pattern 150 is formed by a photo-lithography process on the first gate electrode 110′ and the second polysilicon layer 140 so as to be spaced from each other so as to close and define only the first gate electrode 110′ of the PMOS region and the NMOS region.
Thereafter, as shown in FIG. 1i, the second polysilicon layer 140 around the NMOS region is removed by etching by an RIE method or the like by using the corresponding third photoresist pattern 150 as an etching mask while protecting the formed first gate electrode 110′.
Next, the third photoresist pattern 150 used is removed by a method, such as plasma ashing.
Hence, a second gate electrode 140′ is formed in the NMOS region by the left second polysilicon layer.
As a result, the formation of a dual gate is completed.
However, the above-described conventional method for forming a dual gate of a semiconductor device can have a number of problems.
For example, manufacturing productivity is lowered due to complexity in the manufacturing process because three masking steps of the first to third photoresist patterns 120, 130, and 150 are used.
In particular, to improve the conductivity of the gate electrodes 110′ and 140′, p-type dopant ions are implanted into the gate electrode 110′ of the PMOS region, and n-type dopant ions are implanted into the gate electrode 140′ of the NMOS region. Even in the event of such ion implantation, masking is used, which introduces increased process complexity in due in part to the number of masking steps carried out.
Further, the gate electrodes 110′ and 140′ of the PMOS and NMOS regions are each formed in the same manner, and hence there is a limitation in obtaining performance improvement through different characteristics of each region.